1. Field of the Invention
The present invention relates to a method for programming and verifying the programmed state for multi-level flash memory cells.
2. Description of the Related Art
Multi-level storage refers to the ability of a single memory cell to represent more than a single binary bit of data. A conventional memory cell depicts two states or levels, usually referred to as logic "0" and logic "1". A multi-level cell can represent many states.
Multi-level cell storage is obtainable in flash memory cells because a flash memory cell can be programmed to provide multiple threshold voltage (vt) levels. For example, in FIG. 1 four vt levels are shown, vt0-vt3, and a representation of the state stored by the memory cells can be provided using two binary bits labeled Q1 and Q2 as shown. Using flash memory cells, vt levels programmed can be sustained over time, even after repeated accesses to read data from the cell.
FIG. 2 shows a typical configuration for an integrated circuit including a flash memory array 200 and circuitry enabling programming, erasing, and reading or verifying the programming state for memory cells in the array 200. The flash memory array 200 is composed of individual cells, such as 202. Each cell has a drain connected to a bitline, such as 204. Each bitline is connected to a bitline pull up circuit 206 and column decoder 208. Sources of the array cells are connected to Vss, while gates are each connected by a wordline to a row decoder 210.
The row decoder 210 receives voltage signals from a power supply 212 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor 214. Likewise, the bitline pull up circuit 206 receives voltage signals from the power supply 212 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 214.
The column decoder 208 provides signals from particular bitlines to sense amplifiers or comparators 216 as controlled by a column address signal from processor 214. The sense amplifiers 116 further receive a voltage reference signal from reference 118 to enable reading, as described in more detail below. The outputs from sense amplifiers 216 can be provided to a page buffer 220 which has outputs connected back to processor 214. The outputs of the sense amplifiers 216 can also be connected directly back to the processor 214 if a page buffer 220 is not desired. To program a cell in the flash memory array 200, high gate-to-drain voltage pulses are provided to the cell from power supply 212 while a source of the cell is grounded. For instance, during programming typical gate voltage pulses of 10V are each applied to a cell, while a drain voltage of the cell is set to 5.5V and its source is grounded. This programming procedure results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 200, relatively high negative gate-to-source voltage pulses are applied. For instance, during erase gate voltage pulses of -10V are applied to a cell, while a drain of the cell is set to 5.5V and its source is floated. The large negative gate-to-source voltage pulses reduce the threshold of the cell.
To determine if a cell is programmed or erased to a desired threshold level, a read or verify procedure is applied after each program or erase pulse. During verify, a gate or wordline voltage WL.sub.1 -WL.sub.3 is applied to a cell as illustrated in FIG. 1 The bitline output (BL) from a cell 300 being read is received at an input of one of the sense amplifiers 302 in sense amplifiers 216, as illustrated in FIG. 3. A second input to the sense amplifier 302 is provided from the reference 218. The reference 218 provides a minimal current so that if the wordline voltage WL is greater than the vt level of a cell, the output of sense amplifier 302 will indicate a first state, and if the wordline voltage is less than the vt level of the cell, the output of sense amplifier 302 will indicate a second state. Program or erase pulses are applied with a verify procedure between each pulse until the output of sense amplifier 302 toggles to indicate a desired vt level is obtained.
To enable more rapid reading of a state stored by a memory cell, a page buffer 220 containing latches can be connected to the outputs of sense amplifiers 216, as further shown in FIG. 2, and as shown in detail in FIG. 3. The page buffer 220 reduces read time since the latches of the page buffer 220 store the memory cell state after a first read operation so that subsequent read operations involving the memory cell are not required.
FIG. 3 shows three latches 311-313 of a page buffer 220 coupled to the output of a memory cell 300. If the output of sense amplifier 302 is high, the transistor 340 will turn on and overcome current source 342 and pull down node 350. If the output of sense amplifier 302 is low, the transistor 340 will turn off and current source 342 will pull up node 350. A latch enable signal can be applied to one of transistors 331-333 to connect the node 350 to a respective one of the latches 311-313. The respective latch will then store the state of node 350.
During a verify operation, each latch enable is separately applied to transistors 331-333 depending on the level of the wordline voltage WL applied to the memory cell. For example, for a vt1 level, the latch 311 is enabled by applying an enable signal to transistor 331 and a word line voltage is applied at the WL.sub.1 level as shown in FIG. 1. The latch 311 will then indicate if the threshold of the memory cell 300 is below WL.sub.1 or above WL.sub.1 at vt1, referring to the program states of FIG. 1. Similarly, the latch 312 is enabled using a transistor 332 when a wordline voltage at the WL.sub.2 level is applied to determine if the cell is programmed to vt2, and the latch 313 is enabled using transistor 333 and a wordline voltage WL.sub.3 is applied to determine if a cell is programmed to the vt3 level. The state of the latches 311-313 after applying wordline voltages WL.sub.1 -WL.sub.3 and enabling the appropriate latches indicates the state stored by the memory cell 300.
Note that the wordline levels WL.sub.1 -WL.sub.3 in FIG. 1 are between the vt1-vt3 levels. The hatch marks illustrate a spectrum of vt states for each of the levels vt0-vt3. During a typical program/verify procedure, after each program pulse is applied, one of the word line voltages WL.sub.1 -WL.sub.3 is applied to a cell. When the cell conducts during a verify procedure, the cell is programmed above the desired wordline voltage to one of the levels vt1-vt3 and programming is complete. For an erase procedure, erase pulses are applied until a cell having WL.sub.1 applied as a gate voltage no longer conducts indicating it has a threshold at vt0.
To program an array of cells, all cells are typically erased first. Memory cells are then programmed in an order according to a threshold level to be stored. For instance, all memory cells having a vt1 state are programmed first. Once programming is complete for all memory cells having a vt1 state, programming is performed for all cells having the vt2 state. Once programming for cells having a vt2 state is complete, all cells are programmed having a vt3 state, and so forth.
To facilitate programming, data to be stored in a memory cell can be preloaded into the page buffer latches using signals provided to the preset connection such as the prst0-prst3 connections to latches 311-313 of FIG. 3. For example, a "0" can be preset into latches where it is desired to cause the corresponding flash cell to program to a higher vt level, while a "1" is preset into the remaining latches. The cells having a latch with a "0" state will have programming pulses applied until the latch with a "0" state transitions to a "1" state. For example, loading latch 311 with 0, latch 312 with 1, and latch 313 with 1 and following the above programming procedure will cause the vt of cell 300 to be raised from the erase vt0 level to the vtl level during programming.